1. Field of the Invention
The Direct Synchronization of Synthesized Clock (DSSC) contributes a method, system and apparatus enabling reliable and inexpensive synthesis of inherently stable local clock synchronized accurately to a referencing signal received from an external source.
Such local clock can be synchronized to a referencing frame or a data signal received from wireless or wired communication link and can be utilized for synchronizing local data transmitter or data receiver.
Such DSSC can be particularly useful in OFDM systems such as LTE/WiMAX/WiFI and Powerline/ADSL/VDSL, since it can secure lower power consumption, better noise immunity and much more reliable and faster receiver tuning than those enabled by conventional solutions.
This invention is also directed to providing low cost high accuracy phase and frequency recovery techniques (PFRT) offering significantly better stability and accuracy in synchronizing systems and circuits in multiple fields including communication systems, distributed control, test and measurement equipment, and automatic test equipment.
Such PFRT comprises software controlled clock synchronizer (SCCS) which can be used in multiple fields exemplified above wherein said communication systems include communication networks for wireless or wireline or optical transmissions with very wide ranges of data rates.
The SCCS comprises further novel components such as; programmable phase synthesizers (PS), precision frame phase detectors (FPD) of an incoming wave-form, and noise filtering edge detectors (NFED) for precise recovering of wave-form edges from noisy signals.
Furthermore: since said FPD and NFED define circuits and methods enabling ˜10 times faster and more accurate location systems than conventional solutions, they allow reliable location services for mobile and traffic control applications including fast movements at close ranges in noisy environments unacceptable for solutions.
Still furthermore this invention comprises receiver synchronization techniques (RST), utilizing a referencing frame, recovered from an OFDM composite signal, for synchronizing an OFDM receiver clock to a composite signal transmitter clock.
2. Background Art of Software Controlled Clock Synchronizer
Conventional solutions for software controlled synchronization systems use software controlled digital phase locked loops (DPLLs) for implementing software algorithm minimizing phase errors and providing programmed transfer function between a DPLL output clock and a timing reference.
In conventional solutions said timing reference can be provided:
as a conventional external clock connected to a digital phase detector, which compares it with the local clock in order to produce the digital phase error;
or with time stamp messages sent by an external source, initiating a capture of local clock time and communicating external clock timing corresponding to the captured local timing, wherein software is used for producing said digital phase errors by comparing the captured local timing with the communicated external timing.
However the conventional DPLL configurations have four major limitations listed below:    1. DPLLs are inherently unstable if said timing reference comprises components having frequencies higher than ⅕ of the DPLL bandwidth. Since time stamp messages are sent over regular communication links they are subjected to highly unpredictable time delay variations (TDVs) resulting from collisions between different packet streams sharing a common communication line. Such unpredictable TDVs are bound to introduce timing reference components having unknown frequency spectrums, when said timing reference is provided by exchanging time stamp packages sent over shared communication link. Resulting stability problems cause such conventional DPPL configurations to be highly unreliable in many applications.    2. Conventional digital phase detectors and said software algorithms minimizing phase errors, involve accumulation of phase digitization errors. Such accumulation causes an uncontrolled phase drift of the output clock, when a software error minimization procedure is unable to recognize and eliminate persistent existence of an digitization error corresponding to a lasting unknown frequency error of the output clock.    3. Conventional digital phase detectors; offer resolutions worse than that of phase steps limited by maximum clock frequency of IC technology, and they require complex processing for calculating precise phase skews when highly irregular edges of a reference timing are defined in newly emerging timing protocols such as IEEE 1588. Similarly clock synthesizers have phase steps resolutions bounded by maximum clock frequency of IC technology and furthermore they use frequency synthesis method unable to provide high precision control of phase transients of synthesized clock.    4. Conventional clock synchronization systems require expensive local oscillators, expensive external off-chip analog components, and expensive IC technologies suitable for mixed mode operations; in order to provide highly stable and low jitter synchronization clocks required in industrial control systems and in communication networks. Temperature stable crystal oscillators are major cost contributors exceeding ⅔ of total costs of synchronization systems. However in conventional solutions; low cost highly stable crystal cuts can not be used, since their oscillation frequencies are to low to be transformed into a stable low jitter clock.
Conventional synchronization systems use digital phase detectors which are >5 times less accurate than this inventions FPD, and frequency synthesizers producing uncontrolled phase transients during any frequency switching and introducing 10 times less accurate phase steps than this inventions phase synthesizer PS.
Such frequency synthesizers are based on direct digital frequency synthesis (DDFS) method modifying average frequency of an output clock by periodical removal of a clock pulse from a continues stream of pulses. Since said frequency synthesizers use over 10 times slower phase processing and introduce unknown numbers of 10 times less accurate phase steps than the PS, they are unable to perform any phase synthesis and produce uncontrolled phase transients during frequency switching and introduce much more jitter than the PS.
Consequently; in order to limit phase transients to acceptable levels, said conventional synchronization systems are bound to work in closed loop configurations wherein output clock phase is subtracted from reference clock phase and resulting phase error is minimized by a programmable control unit driving frequency synthesizer producing said output clock
3. Background art of Receiver Synchronization Techniques
Insufficient accuracy of conventional synchronization for OFDM receivers impose major limitations on OFDM communication quality (see Cit. [1] and [2] listed below) and such limitations are compounded by rapidly growing data rates.
Some conventional solutions add specific preambles inserted into composite signal (Cit. [3], [4], [5], and [6]). Such preamble comprises similar parts having known phase (displacement in time) within the preamble.
Such preambles enable detection of symbol boundary time offset, by steps of:
evaluating correlation functions between OFDM signal portions shifted properly in time until such similar preamble parts are detected;
using a phase of local clock frame marked by the similar parts detection and said known phase of such similar parts detected, for estimating time offset of the local frame;
estimating frequency offset of the local clock versus transmitter clock by analyzing said correlation functions between such preamble parts shifted properly in time.
Other synchronization solutions analyze correlation estimates of received pilot preambles or pilot tones with predefined pilot preambles or pilot tones (Cit.[7]), in order to estimate time offset and frequency offset of the local clock frame.
However such use of preambles or pilots; reduces system efficiency by using signal power that could otherwise have been used for transmitting data, and allows limited accuracy only due to such detection and estimates sensitivity to channel interference and insufficient data supplied in the preamble.
There are also pilot-less synchronization techniques. One such pilot-less technique, named maximum likelihood (ML) method (Cit.[8]), utilizes inherent redundancy in OFDM signal, by correlating parts of the signal with other parts having known positioning within frame (cyclic prefix). However; as such pilot-less technique uses statistical methods and depend on transmitted data patterns, they are even less accurate than those using preambles or pilots.
Another pilot-less technique calculates timing offset and frequency offset from displacements of tone phases caused by said timing and frequency offsets (Cit.[9]).
Fundamental deficiency of conventional solutions characterized above is their inability to perform any accurate measurement of frequency offset; due to their reliance on using phase offset observed over single preamble/pilot period only for the frequency offset estimation. Such estimates degraded by unpredictable OFDM channel interference, can not be helped enough by averaging them for as long as each estimate is calculated over single preamble/pilot.
Still other significant deficiency of conventional synchronization is instability of their phase locked loops (used for phase and frequency tracking), caused by changing data patterns and/or unpredictable phase error components introduced into OFDM channel by generally unknown interference.
Such conventional synchronization solutions for OFDM receivers did not succeed in providing reliable and accurate recovery of a referencing frame providing time domain definition of phase and frequency of received OFDM composite frame. However such referencing frame defined in time domain, is essential for achieving accurate control of local oscillator frequency offset and receiver time offset (receiver phase error).
OFDM composite signal has not been originally designed to carry distinctive edges enabling detection of composite frame boundaries, and conventional DFT/IDFT frequency domain processing is not well suited for any accurate detection of such boundaries occurring in time domain either.
Conventional DSP techniques and processors used are not equipped to perform real-time processing of OFDM signal needed to produce such referencing frame maintaining predictable accurate timing relation to the OFDM signal received.
Such major deficiencies of conventional solutions are eliminated by the RST as it is explained in Subsection 2 of BRIEF SUMMARY OF THE INVENTION.